Digital ASIC design

The aim of this module is to illustrate the design flow of an ASIC (Application-Specific Integrated Circuit) in 0.35-micron CMOS technology. The design flow is divided into two main parts: logic synthesis (Design Compiler, Synopsis) based on a behavioral description of the circuit in VHDL, and routing placement (EDI, Cadence) based on the synthesis results. Each design step is validated by simulations (ModelSim, MentorGraphics). The design culminates in the generation of integrated circuit manufacturing masks. 

Knowledge of digital electronics

Knowledge of VHDL language

4 sessions of 3 hours on machine : 

- 2 sessions for a tutorial on the design of a 6-bit binary counter, with performance analysis (circuit size, propagation time, power consumption).

- 2 sessions for the design of a circuit freely chosen by each student, with submission of a design report including a description of the chosen circuit, simulation results and the performance of the designed circuit.