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Joint hardware/software design. Open-source hardware for embedded systems

  • School / Prep

    ENSEIRB-MATMECA

Internal code

EEL9-NUME2

Description

Course :

  • SoC. Codesign.
  • State of the art technology.
  • IP blocks and virtual components.
  • Hardware-software partitioning.
  • Description of codesign implementation with the Quartus Prime tool from Intel (formerly Altera).
  • Description of codesign implementation with AMD's Vivado tool (formerly Xilinx).

TP :

  • Grand TP1: Quartus Prime tool from Intel :
    • Codesign implementation on a Terasic DE10-Standard board with Quartus Prime.
    • Construction of a first SoPC with the NIOS II softcore processor in the Intel Cyclone V FPGA circuit.
    • Construction of a second SoPC with an additional VGA interface.
    • Programming with the C language.
    • Implementation of the µC/OS Real Time kernel II.
    • Software testing of SoPC hardware peripherals without an operating system (bare-metal), then with the µC/OS II Real-Time kernel.
    • Miniprojects (stopwatch, clock).
  • Grand TP2: AMD's Vivado tool:
    • Implementation of codesign on a Digilent ZedBoard with Vivado HLS.
    • Building a SoPC with the ARM Cortex-A9 hardcore processor in the AMD Zynq FPGA circuit.
    • Development in VHDL RTL and integration of a free hardware device (64-bit counter IP block).
    • Programming in C language.
    • Implementation of the Xenomai Cobalt hard real-time Linux extension. Programming with the native API.
    • Software testing of the hardware device created in VHDL RTL under embedded Linux, then under Linux Xenomai Cobalt.
    • Real-time performance and latency measurement.
  • Grand TP3: AMD's Vivado tool:
    • This tutorial links up with the "Advanced digital design float" EN325 course, where HLS high-level synthesis is studied.
    • Implementation of HLS high-level synthesis on a Digilent ZedBoard with Vivado.
    • Creation of an algorithm written in C language (polynomial function).
    • HLS synthesis of the algorithm to create an IP block.
    • Construction of a SoPC with the ARM Cortex-A9 hardcore processor in the AMD Zynq FPGA circuit integrating the IP block obtained by HLS.
    • Programming in C language.
    • Software testing of the hardware device created in HLS under embedded Linux.
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Teaching hours

  • CMLectures1,33h
  • TDMMachine Tutorial16h

Mandatory prerequisites

VHDL language, FPGA circuits, AMD Vivado tool, Intel Quartus Prime tool, C language, Linux, Linux commands, system programming, embedded Linux, Real-Time.

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Bibliography

Handouts

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Assessment of knowledge

Initial assessment / Main session - Tests

Type of assessmentType of testDuration (in minutes)Number of testsTest coefficientEliminatory mark in the testRemarks
Integral Continuous ControlContinuous control1Grades take into account TP reports and participation in these courses (attendance, active participation).