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Processor architecture

  • School / Prep

    ENSEIRB-MATMECA

  • Study level

    Bac + 4

Internal code

ESE8-NUMU1

Description

The aim of this course is to provide students with the necessary knowledge of modern processor architectures and microarchitectures. The RISC-V instruction set is used to illustrate the various mechanisms.
Various concepts are covered:

Instruction set architectures,
Pipelining and dependency problems,
Superscalar microarchitectures,
Caches and memory hierarchy,
Speculation mechanisms.

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Objectives

Skills developed through this module :

  • Analyze and use programmable architecture for embedded systems - level 2
  • Designing and implementing a program written in C/C++ for embedded systems - level 2
  • Designing and implementing a programmable architecture for embedded systems - level 2
  • Designing and implementing a digital architecture for embedded systems - Level 2
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Teaching hours

  • CIIntegrated courses28h

Mandatory prerequisites


EN110: Digital electronics
MI100: Microcontroller architecture
IF126: C language for electronics

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Syllabus


Instruction set architectures.
The pipeline and dependency problems.
Superscalar microarchitectures.
Caches and memory hierarchy.
Speculation mechanisms.

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Further information

Processor architectures, embedded systems

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Bibliography

Online documents

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Assessment of knowledge

Initial assessment / Main session - Tests

Type of assessmentType of testDuration (in minutes)Number of testsTest coefficientEliminatory mark in the testRemarks
Integral Continuous ControlContinuous control