Processor architecture II

This course is a continuation of the first-year module EN114, and aims to reinforce knowledge by covering more advanced techniques relating to processors and memories. The aim of this course is to enable students to understand the most sophisticated multi/many-core systems. Like EN114, the RISC-V instruction set specification is at the heart of this module.1 - Introduction to the notion of pipeline2 - RISC-V pipeline architecture3 - Micro-coded RISC-V architecture4 - Cache memories5 - Superscalar execution6 - Branch prediction7 - OoO (Out-of-Order) execution8 - Register renaming9 - VLIW (Very Long Instruction Word), vector and multithreaded processors10 - Address translation and protection11 - Virtual memory

- EN114 Microprocessors (1st year)

1 - Introduction to pipelining2 - Pipelined RISC-V architecture3 - Micro-coded RISC-V architecture4 - Cache memories5 - Superscalar execution6 - Branch prediction7 - OoO (Out-of-Order) execution8 - Register renaming9 - VLIW (Very Long Instruction Word), vector and multithreaded processors10 - Address translation and protection11 - Virtual memory

Digital electronics

Online documents (no paper copies)