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School / Prep
ENSEIRB-MATMECA
Internal code
EE8EA202
Description
The concept of frequency synthesis is first introduced, along with the challenges and limitations of the function. The various blocks making up a phase-locked loop are then detailed, along with their impact on PLL performance.
Teaching hours
- CIIntegrated courses5h
- TDTutorial4h
Syllabus
1/ PLL Basics2/ Phase Comparators and PLL Operating Modes3/ Loop Filter and PLL Performances 4/ Conclusion
Assessment of knowledge
Initial assessment / Main session - Tests
| Type of assessment | Type of test | Duration (in minutes) | Number of tests | Test coefficient | Eliminatory mark in the test | Remarks |
|---|---|---|---|---|---|---|
| Integral Continuous Control | Continuous control | 1 |