Digital ASIC design

The aim of the module is to give an overview of the design flow of a digital circuit. An introductory lecture (2-3h) gives an overview of digital circuit technologies (CMOS logic, full-custom design, standard cell library, gate arrays, etc.). Emphasis is also placed on the design flows of a digital ASIC, as well as on the issues involved in designing a digital integrated circuit with several million gates (complexity, design flow automation, power consumption, etc.). The remainder of the CI proposes to synthesize a simple counter using logic synthesis tools (Cadence RTL Compiler/ Synopsys design compiler). The circuit is then mapped using a standard CMOS cell library. The resulting circuit is then simulated and verified under time constraints using the Modelsim simulation tool.

VHDL - EN 113 module

- Introduction to the automation of digital circuit design flows
- Independent familiarization with the design_vision tool (synopsys) using a tutorial
- Project on design_vision