School / Prep
ENSEIRB-MATMECA
Internal code
ES7MI205
Description
The aim of this course is to provide students with the necessary knowledge of modern processor architectures and microarchitectures. The RISC-V instruction set is used to illustrate the various mechanisms.
Various concepts are covered:
Instruction set architectures,
Pipelining and dependency problems,
Superscalar microarchitectures,
Caches and memory hierarchy,
Speculation mechanisms.
Teaching hours
- CIIntegrated courses28h
Mandatory prerequisites
EN110: Digital electronics
MI100: Microcontroller architecture
IF126: C language for electronics
Syllabus
Instruction set architectures.
The pipeline and dependency problems.
Superscalar microarchitectures.
Caches and memory hierarchy.
Speculation mechanisms.
Further information
Processor architectures, embedded systems
Bibliography
Online documents
Assessment of knowledge
Initial assessment / Main session - Tests
Type of assessment | Type of test | Duration (in minutes) | Number of tests | Test coefficient | Eliminatory mark in the test | Remarks |
---|---|---|---|---|---|---|
Continuous control | Active Participation | 0.15 | ||||
Continuous control | Minutes | 0.15 | ||||
Final inspection | Written | 60 | 0.7 | without document without calculator |