Test and Verification

The aim of this course is to provide an understanding of the issues involved in verifying digital systems during the design phase. In order to improve design processes and reduce development time, the usual methods used in the design of digital systems are detailed. Finally, these methods are implemented during a sequence of TDs/TPs using the C and VHDL languages.

Proficiency in C/C++ and VHDL is required.

Part 1: System verification issues
Part 2: Verification methods
Part 3: Verification tools for software development.
Part 4: Verification tools for hardware development.

Verification, V-cycle, Software programming (C/C++), Hardware architectures (VHDL), testbench