Joint design on FPGA

Theoretical and practical module for joint design on FPGAs. A project is carried out during all sessions, enabling students to follow the design flow of a heterogeneous system, and to experience the problems of the discipline from the point of view of the embedded system architect, the VHDL developer and the software developer.

VHDL for FPGA
-C/C++
-Computer architecture

Introduction to Codesign
-HW/SW comparison
-System On Chip
-Embedded system architect
-Co-design flow
-Microblaze SoftCore (pipeline, ALU, FSL bus)
-Design reuse
-VHDL coding rules