UE E9SE-A - Hardware architecture and joint design

Level of knowledge :

N1: beginner
N2: intermediate
N3: advanced
N4: expert

The knowledge (skills) expected at the end of the courses of the UE

Understand the design techniques of systems on silicon (SoC) mixing hardware and software by the codesign method: (C1, N3), (C2, N3)
Learn how to implement open-source hardware and software in an embedded system: (C1, N3), (C2, N3)
Learn high-level synthesis techniques for designing systems on silicon (SoC): (C1, N3), (C2, N3)
Learn how to implement high-performance computing machines: (C1, N3), (C2, N3)


Learning outcomes in terms of abilities, skills and attitudes expected at the end of EU courses

Design an FPGA-based silicon system using the codesign method: (C3, N3), (C4, N3), (C5, N2)
Choose open-source hardware and software solutions to design your silicon system: (C3, N3), (C4, N2), (C5, N2)
Design a silicon system on FPGA circuitry using high-level synthesis (HLS) tools: (C3, N3), (C4, N3), (C5, N3)
Implement a system-level hardware description language (systemC): (C3, N3), (C4, N3), (C5, N3)
Implement intensive computing solutions on multi-core system-on-chip and GPGPU with the help of suitable libraries (OpenMP, CUDA....): (C3, N3), (C4, N3), (C5, N3)