Advanced digital design float

The aim of this course is to make engineering students aware of the different levels of abstraction separating system specifications from hardware implementation. The technological target used will be the ZYNQ circuit. This is a System on Chip (SoC) developed by AMD-Xilinx, which combines a general-purpose processor (ARM) with a Field-Programmable Gate Array (FPGA) on a single chip. This architecture combines the advantages of a conventional processor (software flexibility) and an FPGA (hardware acceleration and parallel processing).

The 8 sessions of the module will take place as follows:

- session 1: 1h20 lecture + 2h40 TDM on the Zynq circuit from Xilinx-AMD
objective: after the lecture, an introductory sequence to Vitis IDE coupled with Vivado will enrich the use of the general-purpose ARM processor.

- session 2: 4h00 of TDM on the Xilinx-AMD Zynq
objective: design, integration and operation of VHDL IP blocks integrated on the PL part of the SOC.

Continuous assessment at the end of session 2 on the theme of Zynq and the associated design flow.

- session 3: 1h20 lecture + 2h40 TDM on architecture synthesis (HLS)
objective: after the lecture, an introductory sequence to Vitis HLS coupled with Vivado and Vitis IDE on two pedagogical examples, namely MAC operation and matrix multiplication.

- session 4: 4h00 TDM on architecture synthesis
objective: exploit architecture synthesis to generate finite impulse response (FIR) filter architectures: use of directives and management of data formats.

Continuous assessment at the end of session 4 on the theme of architectural synthesis

- session 5: 1h20 lecture + 2h40 TDM on Introduction to overlay programming with PYNQ
objective: interact with IP blocks described in VHDL or derived from architecture synthesis.

- session 6: 4h00 TDM on Introduction to overlay programming with PYNQ
objective: introduction to data flows (Axi-Stream) and DMA accesses. Use of these concepts to generate finite impulse response filter architectures.

Continuous assessment at the end of session 6 on the theme of the PYNQ approach

- sessions 7 and 8: 8 hours of TDM (day) on an advanced project. The subject is to design and implement an architecture for an advanced digital function.
- description of a reference version of the function in python under Jupyter to be executed under the PYNQ environment;
- use of Vitis-HLS to define a synthesizable behavioral model;
- integration of the dedicated IP under VIVADO;
- generation of the overlay for the PYNQ environment;
- comparison of software and hardware implementations.

Two-page report on the advanced project.

In order to follow this pedagogical sequence, it is necessary to master the development of digital circuits using the VHDL language, as well as the concepts of object programming (C++).

Digital electronics, joint design, system modeling.