School / Prep
ENSEIRB-MATMECA
Internal code
EE7EN201
Description
Integrated circuit description languages:
- Background
- The VHDL language
- Digital circuit synthesis
Teaching hours
- CMLectures4h
- TDTutorial5h
- TDMMachine Tutorial9h
- TIIndividual work6h
Syllabus
Course:
The VHDL language for synthesis
The VHDL language, advanced concepts (generic, package, etc.)
FPGAs, internal architecture of programmable circuits
Synthesis: from VHDL description to FPGA implementation
TDs
Reminder and implementation of the VHDL language in preparation for machine sessions,
Logic synthesis of elementary VHDL components by hand.
Tutorial sessions in CAD environment
Training in tools for VHDL design project (EN202)
Further information
NO EXEMPTION IN 2024-2025
Assessment of knowledge
Initial assessment / Main session - Tests
Type of assessment | Type of test | Duration (in minutes) | Number of tests | Test coefficient | Eliminatory mark in the test | Remarks |
---|---|---|---|---|---|---|
Final inspection | Written | 120 | 0 | without document calculator allowed |
Second chance / Catch-up session - Tests
Type of assessment | Type of test | Duration (in minutes) | Number of tests | Test coefficient | Eliminatory mark in the test | Remarks |
---|---|---|---|---|---|---|
Final test | Written | 120 | 0 | without document calculator allowed |