School / Prep
ENSEIRB-MATMECA
ECTS
7 credits
Internal code
EE7B
Description
Level of knowledge :
N1 : beginner
N2 : intermediate
N3 : confirmed
N4 : expert
Knowledge expected at the end of the course
Acquire the basics of network operation and associated programming methods (C1, N1), (C2, N1)
Acquire the operating principles of FPGA architectures and associated design flows (C1, N2), (C2, N2)
Know and identify the different modes of digital circuit integration: (C1, N2), (C2, N2), (C6, N2)
Learning outcomes in terms of abilities, skills and attitudes expected at the end of the course
Learn to program network applications in C on a UNIX-type operating system: (C3, N1)
Learn the syntax and advanced concepts of the VHDL architecture description language: (C3, N2), (C4, N2)
Master the Xilinx Vivado logic synthesis and simulation environment: (C3, N2), (C5, N2)
Implement a digital architecture project, from architectural specification to debugging on FPGA circuits: (C4, N2), (C5, N2), (C7,N2), (C8,N2)