Digital design

The aim is to carry out a project in VHDL, for the moment based on a lotto.
The objectives are simple but essential:
- to learn autonomy,
- to acquire skills in VHDL,
- to develop a synthetic mind for writing the report,
- to improve English (English is not compulsory, but is highly valued),
- to acquire skills in project presentation with a short oral presentation.

VHDL syntax
State machine
Notion of clock and enable signals

Project on computer with implementation on FPGA board
- Lotto draw on NEXYS 3 board (Spartan6)
- Manual draw with management of recorded numbers and doubles.
- Display of results on 4 7-segment displays.