School / Prep
ENSEIRB-MATMECA
ECTS
4 credits
Internal code
ES8A
Description
Level of knowledge :
N1 : beginner
N2 : intermediate
N3 : confirmed
N4 : expert
The knowledge (skills) expected at the end of EU courses
Understand the internal structure and operation of reconfigurable architectures (C2, N3)
Consolidate the operating principles of FPGA architectures and associated design flows (C2, N3), (C3, N3)
Learning outcomes in terms of abilities, skills and attitudes expected at the end of the course
Organize and carry out, independently over several weeks, the stages of a specific project. Propose solutions for implementing electronic functions and sub-functions (C2, N3) (C3,N3) (C7, N2)(C8,N2).
Learn the syntax and advanced concepts of the VHDL architecture description language: (C3, N3), (C4, N3)
Realize a digital architecture project, from architectural specification to burn-in on FPGA circuits: (C4, N2), (C5, N2), (C7,N2), (C8,N2)